1. Field of the Invention
The invention relates to data processing systems and more particularly to a pipelined microprocessor employing a method and apparatus for interfacing a number of multicycle functional units with a register file such that multiple, multicycle operations take place concurrently.
2. Description of the Related Art
The above-referenced copending patent application Ser. No. 07/630,499 describes a pipelined microprocessor in which multiple functions are performed during each pipeline stage. The microprocessor has a memory coprocessor connected to a MEM interface and a register coprocessor connected to a REG interface. The REG interface and MEM interface are connected to independent read and write ports of a register file. An Instruction Sequencer is connected to an independent write port of the register file, to the REG interface and to the MEM interface. An Instruction Cache supplies the instruction sequencer with at least two instruction words per clock. Single-cycle coprocessors and a multiple-cycle coprocessors are connected to the REG and MEM interfaces. The Instruction Sequencer decodes incoming instruction words from the Cache, and issues up to three instructions on the REG interface, the MEM interface, and/or the branch logic within the Instruction Sequencer.
In U.S. Pat. No. 4,891,753 "Register Scoreboarding on a Microprocessor Chip" by David Budde, et al., granted on Jan. 2, 1990 and assigned to Intel Corporation, there is described apparatus for minimizing idle time when executing an instruction stream in a pipelined microprocessor by using a scoreboarding technique. A microinstruction is placed on a microinstruction bus and a microinstruction valid line is asserted. When a load microinstruction is decoded, a read operation is sent to a bus control logic, the destination register is marked as busy, and execution proceeds to the next current microinstruction. The marking provides an indication as to whether a current instruction can be executed without interfering with the completion of a previous instruction. The marking of registers gives rise to the term "scoreboarding". Execution of the current microinstruction proceeds provided that its source and destination registers are not marked "busy"; otherwise the microinstruction valid line is unasserted immediately after the current microinstruction appears on the microinstruction bus. The current microinstruction is thereby cancelled and must be reissued. When data is returned as the result of a read operation, the destination registers are marked as " not busy".
The above-referenced copending patent application Ser. No. 07/486,407 extends this prior scoreboarding technique to encompass all multiple cycle operations in addition to the load instruction. This is accomplished by providing means for driving a Scbok line to signal that a current microinstruction on the microinstruction bus is valid. Information is then driven on the machine bus during the first phase of a clock cycle. The source operands needed by the instruction are read during the second phase of the clock cycle. The resources needed by operands to execute the instruction are checked to see if they are not busy. The Scbok signal is asserted upon the condition that any one resource needed by the instruction is busy. Means are provided to cause all resources to cancel any work done with respect to executing the instruction to thereby make it appear to the rest of the system that the instruction never was issued. The instruction is then reissued during the next clock cycle.
The above-referenced copending patent applications Ser. No. 07/486,408 and Ser. No. 07/488,254 describe a random access (RAM) register file having multiple independent read ports and multiple independent write ports that provide the on-chip registers to support multiple parallel instruction execution. It also checks and maintains the register scoreboarding logic as described in Ser. No. 07/486,407. The register file contains the macrocode and microcode visible RAM registers. The register file provides a high performance interface to these registers through a multi-ported access structure, allowing four reads and two writes on different registers to occur during the same machine cycle. This register file provides a structure that allows multiple parallel accesses to operands which allows several operations to proceed in parallel.
The above-described patent applications disclose a Reduced Instruction Set Computer (RISC) architecture that achieves greater speed in the form of increased throughput (number of completed tasks per unit of time) and increased speed (reduced time it takes to complete a task). The described microprocessor can issue and execute an instruction per clock cycle and provides a large number of registers on chip.
To take full advantage of the architecture, a processor should be organized so that it has the ability to add application specific modules to meet different user applications and it should be able to execute multiple instructions in one clock cycle while concurrently doing loads and branches.
It is therefore an object of the present invention to provide an interface between the on chip register file and the various functional units connected the register file such that results produced by instructions issued to the functional units can be returned in any arbitrary order to the register file.